Datasheet

Rev. 3.00 Mar 17, 2006 page xxxiv of l
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2) .................. 245
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to DRAM Space in RAS Down Mode................................. 247
Figure 6.82 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read
and Write Accesses to Continuous Synchronous DRAM Space in RAS Down
Mode (SDWCD = 1, CAS Latency 2) ................................................................. 248
Figure 6.83 Example of Timing when Write Data Buffer Function is Used........................... 250
Figure 6.84 Bus Released State Transition Timing................................................................. 253
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface........ 254
Section 7 DMA Controller (DMAC)
Figure 7.1 Block Diagram of DMAC.................................................................................... 260
Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A).......................................... 284
Figure 7.3 Operation in Sequential Mode ............................................................................. 291
Figure 7.4 Example of Sequential Mode Setting Procedure.................................................. 292
Figure 7.5 Operation in Idle Mode........................................................................................ 293
Figure 7.6 Example of Idle Mode Setting Procedure............................................................ 294
Figure 7.7 Operation in Repeat mode ................................................................................... 296
Figure 7.8 Example of Repeat Mode Setting Procedure ....................................................... 297
Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified)......... 299
Figure 7.10 Example of Single Address Mode Setting Procedure
(When Sequential Mode Is Specified) ................................................................. 300
Figure 7.11 Operation in Normal Mode.................................................................................. 302
Figure 7.12 Example of Normal Mode Setting Procedure ...................................................... 303
Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0).............................................. 305
Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1).............................................. 306
Figure 7.15 Operation Flow in Block Transfer Mode............................................................. 307
Figure 7.16 Example of Block Transfer Mode Setting Procedure .......................................... 308
Figure 7.17 Example of DMA Transfer Bus Timing .............................................................. 309
Figure 7.18 Example of Short Address Mode Transfer........................................................... 310
Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal)....................................... 311
Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) ...................................... 312
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)....................... 313
Figure 7.22 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer ............. 314
Figure 7.23 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer 315
Figure 7.24 Example of DREQ Pin Low Level Activated Normal Mode Transfer ................ 316
Figure 7.25 Example of DREQ Pin Low Level Activated Block Transfer Mode Transfer .... 317
Figure 7.26 Example of Single Address Mode Transfer (Byte Read)..................................... 318
Figure 7.27 Example of Single Address Mode (Word Read) Transfer ................................... 319
Figure 7.28 Example of Single Address Mode Transfer (Byte Write).................................... 320