Datasheet

Rev. 3.00 Mar 17, 2006 page xxxiii of l
Figure 6.53 Example of Operation Timing in RAS Down Mode (BE = 1, CAS Latency 2) .. 217
Figure 6.54 Auto Refresh Timing ........................................................................................... 218
Figure 6.55 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) .................. 219
Figure 6.56 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)................... 220
Figure 6.57 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0,
RLW1 = 0, RLW0 = 0)........................................................................................ 221
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)..... 222
Figure 6.59 Synchronous DRAM Mode Setting Timing ........................................................ 223
Figure 6.60 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1......... 225
Figure 6.61 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0......... 227
Figure 6.62 Example of Timing when the Read Data Is Extended by Two States
(DDS = 1, or EDDS = 1, RDXC1 = 0, RDXC0 = 1, CAS Latency 2)................. 228
Figure 6.63 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle).......... 230
Figure 6.64 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle).......... 231
Figure 6.65 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)......... 232
Figure 6.66 Example of Idle Cycle Operation (Write after Read) .......................................... 233
Figure 6.67 Example of Idle Cycle Operation (Read after Write) .......................................... 234
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)...................................... 235
Figure 6.69 Example of DRAM Full Access after External Read (CAST = 0)....................... 235
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....... 236
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode (Write after Read)
(IDLC = 0, RAST = 0, CAST = 0) ...................................................................... 236
Figure 6.72 Example of Synchronous DRAM Full Access after External Read
(CAS Latency 2).................................................................................................. 237
Figure 6.73 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)
(IDLC = 0, CAS Latency 2)................................................................................. 238
Figure 6.74 Example of Idle Cycle Operation in RAS Down Mode (Read in Different Area)
(IDLC = 1, CAS Latency 2)................................................................................. 239
Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, CAS Latency 2)................................................... 240
Figure 6.76 Example of Idle Cycle Operation after DRAM Access
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)....... 241
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0) ........................................ 242
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)..................................................... 243
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)......... 244