Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 292 of 926
REJ09B0283-0300
Sequential mode setting
Set DMABCRH
Set transfer source
and transfer destination
addresses
Set number of transfers
Set DMACR
Read DMABCRL
Set DMABCRL
Sequential mode
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
• Clear the FAE bit to 0 to select short address
mode.
• Specify enabling or disabling of internal
interrupt clearing with the DTA bit.
[2] Set the transfer source address and transfer
destination address in MAR and IOAR.
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
decremented with the DTID bit.
• Clear the RPE bit to 0 to select sequential
mode.
• Specify the transfer direction with the DTDIR
bit.
• Select the activation source with bits DTF3 to
DTF0.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
interrupts with the DTIE bit.
• Set the DTE bit to 1 to enable transfer.
Figure 7.4 Example of Sequential Mode Setting Procedure
7.5.3 Idle Mode
Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In
idle mode, one byte or word is transferred in response to a single transfer request, and this is
executed the number of times specified in ETCR. One address is specified by MAR, and the other