Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 291 of 926
REJ09B0283-0300
Address T
Address B
Transfer
IOAR
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)
DTID
· (2
DTSZ
· (N – 1))
Where: L = Value set in MAR
N = Value set in ETCR
Figure 7.3 Operation in Sequential Mode
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
data transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data
transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or
DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of external requests, SCI transmission complete and
reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts.
Figure 7.4 shows an example of the setting procedure for sequential mode.