Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 288 of 926
REJ09B0283-0300
7.4.3 Activation by Auto-Request
Auto-request is activated by register setting only, and transfer continues to the end. With auto-
request activation, cycle steal mode or burst mode can be selected.
In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is
transferred. DMA and CPU cycles are usually repeated alternately. In burst mode, the DMAC
keeps possession of the bus until the end of the transfer so that transfer is performed continuously.
7.5 Operation
7.5.1 Transfer Modes
Table 7.4 lists the DMAC transfer modes.
Table 7.4 DMAC Transfer Modes
Transfer Mode Transfer Source Remarks
Short
address
mode
Dual address mode
(1) Sequential mode
• Memory address incremented or
decremented by 1 or 2
• Number of transfers:
1 to 65,536
(2) Idle mode
• Memory address fixed
• Number of transfers:
1 to 65,536
(3) Repeat mode
• Memory address incremented or
decremented by 1 or 2
• Continues transfer after sending
number of transfers (1 to 256) and
restoring the initial value
• TPU channel 0 to 5
compare match/input
capture A interrupt
• SCI transmission complete
interrupt
• SCI reception complete
interrupt
• A/D converter conversion
end interrupt
• External request
• Up to 4 channels can
operate independently
• External request
applies to channel B
only
• Single address mode
applies to channel B
only
Single address mode
• 1-byte or 1-word transfer for a single
transfer request
• 1-bus cycle transfer by means of
DACK pin instead of using address
for specifying I/O
• Sequential mode, idle mode, or
repeat mode can be specified
• External request