Datasheet

Rev. 3.00 Mar 17, 2006 page xxxii of l
Figure 6.23 Example of Access Timing when RAS Signal Goes Low from Beginning
of T
r
State (CAST = 0)......................................................................................... 178
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0)........................................................................................ 179
Figure 6.25 Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0)... 180
Figure 6.26 Example of Wait State Insertion Timing (2-State Column Address Output)....... 182
Figure 6.27 Example of Wait State Insertion Timing (3-State Column Address Output)....... 183
Figure 6.28 2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ....... 184
Figure 6.29 Example of 2-CAS DRAM Connection............................................................... 185
Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0)............................ 186
Figure 6.31 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1)............................ 187
Figure 6.32 Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) ..... 188
Figure 6.33 Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0).......... 189
Figure 6.34 RTCNT Operation ............................................................................................... 190
Figure 6.35 Compare Match Timing....................................................................................... 191
Figure 6.36 CBR Refresh Timing ........................................................................................... 191
Figure 6.37 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ............. 192
Figure 6.38 Example of CBR Refresh Timing (CBRM = 1)................................................... 193
Figure 6.39 Self-Refresh Timing............................................................................................. 194
Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States............................................................................................................ 195
Figure 6.41 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0)........................................................................................ 196
Figure 6.42 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)........................................................................................ 197
Figure 6.43 Relationship between φ and SDRAMφ
(when PLL frequency multiplication factor is ×1 or ×2) ..................................... 202
Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1)......................... 203
Figure 6.45 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) ........................... 205
Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)....................................... 207
Figure 6.47 Example of Timing with Two-State Precharge Cycle
(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)......................................... 209
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is
Disabled (SDWCD = 1)....................................................................................... 210
Figure 6.49 DQMU and DQML Control Timing
(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)................................. 211
Figure 6.50 DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)........................................................ 212
Figure 6.51 Example of DQMU and DQML Byte Control..................................................... 213
Figure 6.52 Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2)....... 215