Datasheet

Rev. 3.00 Mar 17, 2006 page xxxi of l
Figure 4.4 Operation when SP Value Is Odd ........................................................................ 83
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller ................................................................ 86
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 ...................................................... 102
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 0.................................................................................................... 109
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt
Control Mode 2.................................................................................................... 111
Figure 5.5 Interrupt Exception Handling............................................................................... 113
Figure 5.6 DTC, DMAC, and Interrupt Controller................................................................ 116
Figure 5.7 Contention between Interrupt Generation and Disabling..................................... 118
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller........................................................................ 122
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)..................... 132
Figure 6.3 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0)............................................. 134
Figure 6.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)......................................... 144
Figure 6.5 CAS Latency Control Cycle Disable Timing during Continuous Synchronous
DRAM Space Write Access (for CAS Latency 2)............................................... 148
Figure 6.6 Area Divisions ..................................................................................................... 153
Figure 6.7 CSn Signal Output Timing (n = 0 to 7)................................................................ 158
Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space)........................ 159
Figure 6.9 Access Sizes and Data Alignment Control (16-bit Access Space)....................... 159
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space........................................................ 161
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space........................................................ 162
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) ....... 163
Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access)......... 164
Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access)............................. 165
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) ....... 166
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access)......... 167
Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access)............................. 168
Figure 6.18 Example of Wait State Insertion Timing ............................................................. 170
Figure 6.19 Example of Read Strobe Timing.......................................................................... 171
Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended.................. 172
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0) ........................................ 176
Figure 6.22 Example of Access Timing with 3-State Column Address Output Cycle
(RAST = 0) .......................................................................................................... 177