Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 272 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
1101: Activated by TPU channel 5 compare
match/input capture A interrupt
1110: Setting prohibited
1111: Setting prohibited
The same factor can be selected for more than
one channel. In this case, activation starts with
the highest-priority channel according to the
relative channel priorities. For relative channel
priorities, see section 7.5.12, Multi-Channel
Operation.
Legend:
x: Don't care
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL)
DMABCR controls the operation of each DMAC channel. The bit functions in the DMACR
registers differ according to the transfer mode.
Short Address Mode:
• DMABCRH
Bit Bit Name Initial Value R/W Description
15 FAE1 0 R/W Full Address Enable 1
Specifies whether channel 1 is to be used in
short address mode or full address mode. In
short address mode, channels 1A and 1B can
be used as independent channels.
0: Short address mode
1: Full address mode
14 FAE0 0 R/W Full Address Enable 0
Specifies whether channel 0 is to be used in
short address mode or full address mode. In
short address mode, channels 0A and 0B can
be used as independent channels.
0: Short address mode
1: Full address mode