Datasheet

Rev. 3.00 Mar 17, 2006 page xxx of l
Figures
Section 1 Overview
Figure 1.1 H8S/2678 Group Internal Block Diagram ........................................................... 3
Figure 1.2 H8S/2678R Group Internal Block Diagram......................................................... 4
Figure 1.3 H8S/2678 Group Pin Arrangement...................................................................... 5
Figure 1.4 H8S/2678R Group Pin Arrangement................................................................... 6
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode) ............................................................. 25
Figure 2.2 Stack Structure in Normal Mode ......................................................................... 25
Figure 2.3 Exception Vector Table (Advanced Mode) ......................................................... 26
Figure 2.4 Stack Structure in Advanced Mode ..................................................................... 27
Figure 2.5 Memory Map ....................................................................................................... 28
Figure 2.6 CPU Registers...................................................................................................... 29
Figure 2.7 Usage of General Registers.................................................................................. 30
Figure 2.8 Stack .................................................................................................................... 31
Figure 2.9 General Register Data Formats (1) ...................................................................... 34
Figure 2.9 General Register Data Formats (2) ...................................................................... 35
Figure 2.10 Memory Data Formats......................................................................................... 36
Figure 2.11 Instruction Formats (Examples)........................................................................... 48
Figure 2.12 Branch Address Specification in Memory Indirect Mode.................................... 52
Figure 2.13 State Transitions................................................................................................... 56
Section 3 MCU Operating Modes
Figure 3.1 H8S/2676 Memory Map (1)................................................................................. 65
Figure 3.1 H8S/2676 Memory Map (2)................................................................................. 66
Figure 3.1 H8S/2676 Memory Map (3)................................................................................. 67
Figure 3.1 H8S/2676 Memory Map (4)................................................................................. 68
Figure 3.2 H8S/2675 Memory Map (1)................................................................................. 69
Figure 3.2 H8S/2675 Memory Map (2)................................................................................. 70
Figure 3.3 H8S/2673 Memory Map (1)................................................................................. 71
Figure 3.3 H8S/2673 Memory Map (2)................................................................................. 72
Figure 3.4 H8S/2670 Memory Map ...................................................................................... 73
Figure 3.5 H8S/2674R Memory Map.................................................................................... 74
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled) ....................... 78
Figure 4.2 Reset Sequence (Advanced Mode with On-Chip ROM Disabled) ...................... 79
Figure 4.3 Stack Status after Exception Handling................................................................. 82