Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 266 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
5 RPE 0 R/W Repeat Enable
Used in combination with the DTIE bit in
DMABCR to select the mode (sequential, idle,
or repeat) in which transfer is to be performed.
• When DTIE = 0 (no transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in repeat mode
• When DTIE = 1 (with transfer end interrupt)
0: Transfer in sequential mode
1: Transfer in idle mode
4 DTDIR 0 R/W Data Transfer Direction
Used in combination with the SAE bit in
DMABCR to specify the data transfer direction
(source or destination). The function of this bit
is therefore different in dual address mode and
single address mode.
• When SAE = 0
0: Transfer with MAR as source address and
DACK pin as write strobe
1: Transfer with DACK pin as read strobe and
MAR as destination address
• When SAE = 1
0: Transfer with MAR as source address and
IOAR as destination address
1: Transfer with IOAR as source address and
MAR as destination address
3
2
1
0
DTF3
DTF2
DTF1
DTF0
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Factor 3 to 0
These bits select the data transfer factor
(activation source). There are some differences
in activation sources for channel A and channel
B.