Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 258 of 926
REJ09B0283-0300
6.14.3 External Bus Release Function and CBR Refreshing/Auto Refreshing
CBR refreshing/auto refreshing cannot be executed while the external bus is released. Setting the
BREQOE bit to 1 in BCR beforehand enables the BREQO signal to be output when a CBR
refresh/auto refresh request is issued.
Note: In the H8S/2678 Group, the auto refresh control is not supported.
6.14.4 BREQO
BREQOBREQO
BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
6.14.5 Notes on Usage of the Synchronous DRAM
Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the
synchronous DRAM interface. Do not change the DCTL pin during operation.
Connection Clock: Be sure to set the clock to be connected to the synchronous DRAM to
SDRAMφ.
WAIT
WAITWAIT
WAIT Pin: In the continuous synchronous DRAM space, insertion of the wait state by the WAIT
pin is disabled regardless of the setting of the WAITE bit in BCR.
Bank Control: This LSI cannot carry out the bank control of the synchronous DRAM. All banks
are selected.
Burst Access: The burst read/burst write mode of the synchronous DRAM is not supported. When
setting the mode register of the synchronous DRAM, set to the burst read/single write and set the
burst length to 1.
CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit
to 0 in the DRAMCR.