Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 254 of 926
REJ09B0283-0300
CPU
cycle
External bus released state
External space read
T
1
T
2
φ
Address bus
DQMU, DQML
BREQ
BACK
BREQO
High-Z
High-Z
High-Z
NOP PALL NOP NOP
[1] [2] [3] [5][4] [6][8]
[7] [9]
[1] Low level of BREQ signal is sampled at rise of f.
[2] PLL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
Data bus
High-Z
Precharge-sel
High-Z
WE
High-Z
RAS
CKE
High-Z
CAS
High-Z
SDRAMφ
Row
address
Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface