Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 253 of 926
REJ09B0283-0300
6.11.3 Transition Timing
Figure 6.84 shows the timing for transition to the bus released state.
CPU
cycle
External bus released state
External space
access cycle
T
1
T
2
φ
Address bus
HWR, LWR
BREQ
BACK
BREQO
High-Z
High-Z
High-Z
High-Z
High-Z
[1] [2] [3] [5][4] [6]
[7] [8]
[1] Low level of BREQ signal is sampled at rise of ø.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
bus release while BREQOE bit is set to 1, BREQO signal goes low.
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
Data bus
AS
RD
Figure 6.84 Bus Released State Transition Timing
Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM
interface.