Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 250 of 926
REJ09B0283-0300
T
1
Internal address bus
A23 to A0
External write cycle
HWR, LWR
T
2
T
W
T
W
T
3
On-chip memory read Internal I/O register read
Internal read signal
CSn
D15 to D0
External address
Internal memory
External space
write
Internal I/O register address
φ
Figure 6.83 Example of Timing when Write Data Buffer Function is Used
6.11 Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters except the EXDMAC continue to operate as long
as there is no external access. If any of the following requests are issued in the external bus
released state, the BREQO signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode