Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 247 of 926
REJ09B0283-0300
Previous Access Next Access ICIS2
*
ICIS1 ICIS0 DRMI IDLC Idle cycle
0 ————Disabled
1 ———0 1 state inserted
Normal space read
1 2 states inserted
0 ————Disabled
1 ———0 1 state inserted
DRAM/continuous
synchronous DRAM
*
space write
DRAM/continuous
synchronous DRAM
*
space read
1 2 states inserted
Note: * In the H8S/2678 Group, the synchronous DRAM interface is not supported.
Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of
consecutive read and write operations in DRAM/continuous synchronous DRAM space burst
access. Figures 6.81 and 6.82 show an example of the timing for idle cycle insertion in the case of
consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
c2
DRAM space writeDRAM space read
T
c2
T
i
T
c1
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Note: n = 2 to 5
φ
Figure 6.81 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and
Write Accesses to DRAM Space in RAS Down Mode