Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 246 of 926
REJ09B0283-0300
Table 6.11 Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space
Previous Access Next Access ICIS2
*
ICIS1 ICIS0 DRMI IDLC Idle cycle
— 0 ———Disabled
— 1 ——0 1 state inserted
Normal space read
(different area)
1 2 states inserted
— 0 ———Disabled
— 1 ——0 1 state inserted
DRAM/continuous
synchronous DRAM
*
space read
1 2 states inserted
——0 ——Disabled
——1 — 0 1 state inserted
Normal space write
1 2 states inserted
——0 ——Disabled
——1 — 0 1 state inserted
Normal space read
DRAM/continuous
synchronous DRAM
*
space write
1 2 states inserted
— 0 ———Disabled
— 1 — 0 — Disabled
1 0 1 state inserted
Normal space read
1 2 states inserted
— 0 ———Disabled
— 1 — 0 — Disabled
1 0 1 state inserted
DRAM/continuous
synchronous DRAM
*
space read
1 2 states inserted
——0 ——Disabled
——10— Disabled
1 0 1 state inserted
Normal space write
1 2 states inserted
——0 ——Disabled
——10— Disabled
1 0 1 state inserted
DRAM/continuous
synchronous DRAM
*
space read
DRAM/continuous
synchronous DRAM
*
space write
1 2 states inserted
0 ————Disabled
1 ———0 1 state inserted
Normal space read
1 2 states inserted
0 ————Disabled
1 ———0 1 state inserted
Normal space write
DRAM/continuous
synchronous DRAM
*
space read
1 2 states inserted