Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 245 of 926
REJ09B0283-0300
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
c2
T
3
T
c1
Continuous synchronous
DRAM space write External space read
Continuous synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
HWR, LWR
CKE
High
PALL ACTV NOP WRIT NOP
NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
External address
External address
Column
address
Column address 2
Row
address
Row
address
Column
address
Figure 6.80 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)
Table 6.11 shows whether there is an idle cycle insertion or not in the case of mixed accesses to
normal space and DRAM space/continuous synchronous DRAM space.