Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 244 of 926
REJ09B0283-0300
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
T
3
T
i
T
c1
Continuous synchronous
DRAM space read External space read
Continuous synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
CKE
High
PALL ACTV READ NOP
NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
External address
External address
Column address 1 Column address 2
Row
address
Row
address
Column
address
Figure 6.79 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)
• Normal space access after a continuous synchronous DRAM space write access
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is
not in accordance with the DRMI bit in DRACCR.
Figure 6.80 shows an example of idle cycle operation when the ICIS2 bit is set to 1.