Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 242 of 926
REJ09B0283-0300
T
p
Address bus
φ
RD
RAS
HWR, LWR
UCAS, LCAS
External write
Idle cycle
Data bus
T
r
T
c1
T
c2
T
1
DRAM space readDRAM space read
T
2
T
c2
T
3
T
i
T
c1
Figure 6.77 Example of Idle Cycle Operation after DRAM Access
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)
• Normal space access after DRAM space write access
While the ICIS2 bit is set to 1 in BCR (there is no ICRS2 bit in the H8S/2678 Group, therefore
this setting cannot be made) and a normal space read access occurs after DRAM space write
access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be
inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in
DRACCR. Figure 6.78 shows an example of idle cycle operation when the ICIS2 bit is set to 1.