Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 240 of 926
REJ09B0283-0300
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
T
3
T
c1
Continuous synchronous
DRAM space read External space read
Continuous synchronous
DRAM space write
T
2
T
i
T
1
RAS
CAS
WE
RD
HWR, LWR
CKE
High
High
PALL ACTV READ NOP
NOPWRIT
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
Row
address
Row
address
Column
address
External address
External address
Column address 1 Column address 2
Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, CAS Latency 2)
Idle Cycle in Case of Normal Space Access after DRAM Space Access:
• Normal space access after DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is
disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to
1. The conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.76 and 6.77 show examples of
idle cycle operation when the DRMI bit is set to 1.