Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 237 of 926
REJ09B0283-0300
Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space
Access: In a continuous synchronous DRAM space access following a normal space access, the
settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of
consecutive reads in different areas, for example, if the second read is a full access to continuous
synchronous DRAM space, only T
p
cycle is inserted, and T
i
cycle is not. The timing in this case is
shown in figure 6.72.
Note: In the H8S/2678 Group, the synchronous DRAM interface is not supported.
T
1
Address bus
φ
Column address
Row
address
Row
address
Column
address
Data bus
T
2
T
3
T
p
T
r
T
c2
External space read Synchronous DRAM space read
T
cl
T
c1
RAS
CAS
WE
RD
CKE
PALL ACTV NOP
NOP READ
DQMU, DQML
Precharge-sel
Figure 6.72 Example of Synchronous DRAM Full Access after External Read
(CAS Latency 2)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid
and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML
differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.73