Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 236 of 926
REJ09B0283-0300
T
p
Address bus
φ
RD
RAS
UCAS, LCAS
External read
Idle cycle
Data bus
T
r
T
c1
T
c2
T
1
DRAM space readDRAM space read
T
2
T
c2
T
3
T
i
T
c1
Figure 6.70 Example of Idle Cycle Operation in RAS Down Mode
(Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0)
T
p
Address bus
φ
RD
RAS
HWR
UCAS, LCAS
External read
Idle cycle
Data bus
T
r
T
c1
T
c2
T
1
DRAM space writeDRAM space read
T
2
T
c2
T
3
T
i
T
c1
Figure 6.71 Example of Idle Cycle Operation in RAS Down Mode
(Write after Read) (IDLC = 0, RAST = 0, CAST = 0)