Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 235 of 926
REJ09B0283-0300
T
1
Address bus
φ
RD
Bus cycle A
T
2
T
3
T
1
T
2
Bus cycle B
Overlap period between CS (area B)
and RD may occur
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Address bus
Idle cycle
φ
Bus cycle A
T
2
T
3
T
i
T
1
Bus cycle B
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
T
2
CS (area A)
CS (area B)
RD
CS (area A)
CS (area B)
Figure 6.68 Relationship between Chip Select (CS
CSCS
CS) and Read (RD
RDRD
RD)
Idle Cycle in Case of DRAM Space Access after Normal Space Access: In a DRAM space
access following a normal space access, the settings of bits ICIS2 (not available in the H8S/2678
Group), ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in
different areas, for example, if the second read is a full access to DRAM space, only a T
p
cycle is
inserted, and a T
i
cycle is not. The timing in this case is shown in figure 6.69.
T
1
Address bus
φ
RD
External read
Data bus
T
2
T
3
T
p
T
r
DRAM space read
T
c1
T
c2
Figure 6.69 Example of DRAM Full Access after External Read
(CAST = 0)
In burst access in RAS down mode, the settings of bits ICIS2
(not available in the H8S/2678
Group)
, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is
illustrated in figures 6.70 and 6.71.