Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 227 of 926
REJ09B0283-0300
T
p
φ
SDRAM
φ
RAS
Read
CAS
WE
CKE
PALL ACTV READ NOP
DQMU, DQML
Data bus
Address bus
T
r
T
c1
T
cl
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP NOPWRIT
DQMU, DQML
DACK or RDACK
Data bus
High
Figure 6.61 Example of DACK
DACKDACK
DACK/EDACK
EDACKEDACK
EDACK Output Timing when DDS = 0 or EDDS = 0