Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 224 of 926
REJ09B0283-0300
6.7.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM
Interface
When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output
timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous
DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits
select whether or not burst access is to be performed. The establishment time for the read data can
be extended in the clock suspend mode irrespective of the settings of the DDS and EDDS bits.
(1) Output Timing of DACK
DACKDACK
DACK or EDACK
EDACKEDACK
EDACK
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the synchronous DRAM interface, the DACK or EDACK
output goes low from the T
c1
state.
Figure 6.60 shows the DACK or EDACK output timing for the synchronous DRAM interface
when DDS = 1 or EDDS = 1.