Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 222 of 926
REJ09B0283-0300
T
Rc2
φ
SDRAM φ
RAS
CAS
WE
CKE
NOP PALL NOPACTV NOP NOP
DQMU, DQML
Data bus
Address bus
T
Rp1
T
Rp2
T
p
T
r
T
c1
T
cl
T
c2
Row address Column address Column address
Precharge-sel
Row address
Continuous synchronous DRAM space write
Software
standby
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone
(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped
mode is entered, in which the bus controller and I/O port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected externally and DRAM data is to be retained in sleep mode, the
ACSE bit must be cleared to 0 in MSTPCR.
Software Standby: When a transition is made to normal software standby, the PLL command is
not output. If synchronous DRAM is connected and DRAM data is to be retained in software
standby, self-refreshing must be set.