Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 221 of 926
REJ09B0283-0300
When using self-refresh mode, the OPE bit must not be cleared to 0 in SBYCR.
T
Rp
SDRAM
φ
Precharge-sel
Address bus
T
Rr
CAS
Software standby
T
Rc2
WE
CKE
RAS
NOPSELFPALL
φ
Figure 6.57 Self-Refresh Timing
(TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0)
In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing
self-refreshing and the next command is specified. A setting can be made in bits TPCS2 to TPCS0
in REFCR to make the precharge time after self-refreshing from 1 to 7 states longer than the
normal precharge time. In this case, too, normal precharging is performed according to the setting
of bits TPC1 and TPC0 in DRACCR, and therefore a setting should be made to give the optimum
post-self-refresh precharge time, including this time. Figure 6.58 shows an example of the timing
when the precharge time after self-refreshing is extended by 2 states.