Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 220 of 926
REJ09B0283-0300
When the interval specification from the REF command to the ACTV cannot be satisfied, setting
the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh
cycle. Set the optimum number of waits according to the synchronous DRAM connected and the
operating frequency of this LSI. Figure 6.56 shows the timing when one wait state is inserted.
T
Rp
φ
SDRAMφ
RAS
CAS
WE
CKE
PALL REF
NOP
Address bus
T
Rr
T
Rr1
T
Rcw
T
Rc2
Precharge-sel
High
Figure 6.56 Auto Refresh Timing
(TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1)
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for synchronous DRAM
as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within
the synchronous DRAM.
To select self-refreshing, set the RFSHE bit to 1 in REFCR. When a SLEEP instruction is
executed to enter software standby mode, the SELF command is issued, as shown in figure 6.57.
When software standby mode is exited, the SLFRF bit in REFCR is cleared to 0 and self-refresh
mode is exited automatically. If an auto refresh request occurs when making a transition to
software standby mode, auto refreshing is executed, then self-refresh mode is entered.