Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 219 of 926
REJ09B0283-0300
When the interval specification from the PLL command to the REF command cannot be satisfied,
setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after
the T
Rp
cycle that is set by the TPC1 and TPC0 bits of DRACCR. Set the optimum number of
waits according to the synchronous DRAM connected and the operating frequency of this LSI.
Figure 6.55 shows the timing when one wait state is inserted. Since the setting of bits TPC1 and
TPC0 of DRACCR is also valid in refresh cycles, the command interval can be extended by the
RCW1 and RCW0 bits after the precharge cycles.
T
Rp1
φ
SDRAMφ
RAS
CAS
WE
CKE
PALL NOP REF NOP
Address bus
T
Rp2
T
Rrw
T
Rr
T
Rc1
T
Rc2
Precharge-sel
High
Figure 6.55 Auto Refresh Timing
(TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1)