Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 217 of 926
REJ09B0283-0300
T
p
Address bus External address Column address Column address 2
External address
Row
address
Column
address
Data bus
T
r
T
c1
T
cl
T
c2
T
c1
T
c2
Continuous synchronous
DRAM space read
Continuous synchronous
DRAM space read
External
space read
T
2
T
cl
T
1
RAS
CAS
WE
CKE
High
PALL ACTV READ NOP
NOPREAD
DQMU, DQML
Precharge-sel
Row
address
φ
Figure 6.53 Example of Operation Timing in RAS Down Mode
(BE = 1, CAS Latency 2)
6.7.13 Refresh Control
This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used.
In addition, self-refreshing can be executed when the chip enters the software standby state.
Refresh control is enabled when any area is designated as continuous synchronous DRAM space
in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.