Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 216 of 926
REJ09B0283-0300
RAS Down Mode: Even when burst operation is selected, it may happen that access to continuous
synchronous DRAM space is not continuous, but is interrupted by access to another space. In this
case, if the row address active state is held during the access to the other space, the read or write
command can be issued without ACTV command generation similarly to DRAM RAS down
mode.
To select RAS down mode, set the BE bit to 1 in DRAMCR regardless of the RCDM bit settings.
The operation corresponding to DRAM RAS up mode is not supported by this LSI.
Figure 6.53 shows an example of the timing in RAS down mode.
Note, however, the next continuous synchronous DRAM space access is a full access if:
• a refresh operation is initiated in the RAS down state
• self-refreshing is performed
• the chip enters software standby mode
• the external bus is released
• the BE bit is cleared to 0
• the mode register of the synchronous DRAM is set
There is synchronous DRAM in which time of the active state of each bank is restricted. If it is not
guaranteed that other row address are accessed in a period in which program execution ensures the
value (software standby, sleep, etc.), auto refresh or self refresh must be set, and the restrictions of
the maximum active state time of each bank must be satisfied. When refresh is not used, programs
must be developed so that the bank is not in the active state for more than the specified time.