Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 210 of 926
REJ09B0283-0300
6.7.10 Bus Cycle Control in Write Cycle
By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (T
c1
) that is
inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled.
Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to
synchronous DRAM read access. Figure 6.48 shows the write access timing when the CAS latency
control cycle is disabled.
T
p
φ
SDRAMφ
RAS
CAS
WE
CKE
PALL ACTV WRITNOP
DQMU, DQML
Data bus
Address bus
T
r
T
c1
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
Figure 6.48 Example of Write Access Timing when CAS Latency Control Cycle Is Disabled
(SDWCD = 1)