Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 207 of 926
REJ09B0283-0300
T
p
φ
SDRAM φ
RAS
Read
CAS
WE
CKE
PALL ACTV NOP READ NOP
DQMU, DQML
Data bus
Address bus
T
r
T
rw
T
c1
T
cl
T
c2
Row address
Column
address
Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP NOPWRIT
DQMU, DQML
Data bus
High
Figure 6.46 Example of Access Timing when Row Address Output Hold State Is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2)