Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 203 of 926
REJ09B0283-0300
T
p
φ
SDRAMφ
RAS
Read
CAS
WE
CKE
PALL ACTV READ NOP
DQMU, DQML
Data bus
Address bus
T
r
T
c1
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL ACTV NOP WRIT
DQMU, DQML
Data bus
High
Figure 6.44 Basic Access Timing of Synchronous DRAM (CAS Latency 1)