Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 199 of 926
REJ09B0283-0300
Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all
bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT),
and mode-register write (MRS). Commands for bank control cannot be used.
6.7.2 Address Multiplexing
With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the
upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0 and
the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used.
Table 6.8 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
DRAMCR Address Pins
MXC2 MXC1 MXC0
Shift
Size
A23 to
A16
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 x x Reserved (setting prohibited)
0 8 bits A23 to
A16
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A80
1 9 bits A23 to
A16
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
0 10 bits
A23 to
A16
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
Row
address
1
1
1 11 bits
A23 to
A16
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
0 x x Reserved (setting prohibited)
0 —
A23 to
A16
PPPPPPPA8A7A6A5A4A3A2A1A00
1 — A23 to
A16
PPPPPPA9A8A7A6A5A4A3A2A1A0
0 — A23 to
A16
PPPPPA10A9A8A7A6A5A4A3A2A1A0
Column
address
1
1
1 — A23 to
A16
PPPPA11A10A9A8A7A6A5A4A3A2A1A0
Legend:
X: Don’t care
P: Precharge-sel