Datasheet

Section 6 Bus Controller (BSC)

Rev. 3.00 Mar 17, 2006 page 198 of 926

REJ09B0283-0300

6.7 Synchronous DRAM Interface

In the H8S/2678R Group, external address space areas 2 to 5 can be designated as continuous

synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous

DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous

DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.

Synchronous DRAM of CAS latency 1 to 4 can be connected.

Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.

6.7.1 Setting Continuous Synchronous DRAM Space

Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to

RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and

synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings

are and continuous area (areas 2 to 5).

Table 6.7 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM

Space

RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2

0 1 Normal space Normal space Normal space DRAM space

0 Normal space Normal space DRAM space DRAM space

1 DRAM space DRAM space DRAM space DRAM space

0 Continuous synchronous DRAM space0

1 Mode settings of synchronous DRAM

0 Reserved (setting prohibited)

1 Continuous DRAM space

With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE

signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is

used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous

synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for

the continuous synchronous DRAM are invalid.

Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and

address-precharge-setting command (Prechrge-sel) output on the upper column addresses.