Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 197 of 926
REJ09B0283-0300
When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single
address transfer mode, full access (normal access) is always performed. With the DRAM interface,
the DACK or EDACK output goes low from the T
r
state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing DRAM space.
Figure 6.42 shows the DACK or EDACK output timing for the DRAM interface when DDS = 0 or
EDDS = 0.
T
p
φ
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
DACK or EDACK
Address bus
T
r
T
c1
T
c2
Note: n = 2 to 5
T
c3
Row address Column address
High
High
Figure 6.42 Example of DACK
DACKDACK
DACK/EDACK
EDACKEDACK
EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1)