Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 196 of 926
REJ09B0283-0300
or EXDMAC single address mode at the same time, these bits select whether or not burst access is
to be performed.
When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only,
irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low
from the T
c1
state.
Figure 6.41 shows the DACK or EDACK output timing for the DRAM interface when DDS = 1 or
EDDS = 1.
T
p
φ
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
DACK or EDACK
Address bus
T
r
T
c1
T
c2
Note: n = 2 to 5
Row address Column address
High
High
Figure 6.41 Example of DACK
DACKDACK
DACK/EDACK
EDACKEDACK
EDACK Output Timing when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0)