Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 184 of 926
REJ09B0283-0300
6.6.10 Byte Access Control
When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the
control signals needed for byte access. Figure 6.28 shows the control timing for 2-CAS access, and
figure 6.29 shows an example of 2-CAS DRAM connection.
T
p
High-Z
φ
RASn (CSn)
UCAS
LCAS
WE (HWR)
OE (RD)
Upper data bus
Lower data bus
Address bus
T
r
T
c1
T
c2
Note: n = 2 to 5
Row address Column address
Write data
High
High
Figure 6.28 2-CAS Control Timing
(Upper Byte Write Access: RAST = 0, CAST = 0)