Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 182 of 926
REJ09B0283-0300
By program wait
T
p
Address bus
φ
WAIT
T
r
T
c1
T
w
T
w
T
c2
By WAIT pin
RASn (CSn)
Read
Write
UCAS, LCAS
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Row address Column address
High
High
Notes: Downward arrows indicate the timing of WAIT pin sampling.
n = 2 to 5
Figure 6.26 Example of Wait State Insertion Timing
(2-State Column Address Output)