Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 176 of 926
REJ09B0283-0300
6.6.5 Basic Timing
Figure 6.21 shows the basic access timing for DRAM space.
The four states of the basic timing consist of one T
p
(precharge cycle) state, one T
r
(row address
output cycle) state, and the T
c1
and two T
c2
(column address output cycle) states.
T
p
φ
RASn (CSn)
Read
Write
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Address bus
T
r
T
c1
T
c2
Row address
High
High
Column address
Note: n = 2 to 5
Figure 6.21 DRAM Basic Access Timing (RAST = 0, CAST = 0)
When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When
connecting DRAM provided with an EDO page mode, the OE signal should be connected to the