Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 172 of 926
REJ09B0283-0300
Figure 6.20 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
T
h
Address bus
φ
T
1
T
2
T
3
T
t
Bus cycle
Data bus
HWR, LWR
Write
Data bus
RD
CSn
AS
Read
(when
RDNn = 0)
Read data
Write data
Figure 6.20 Example of Timing when Chip Select Assertion Period Is Extended
Both extension state T
h
inserted before the basic bus cycle and extension state T
t
inserted after the
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or non-
insertion can be specified for the T
h
state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
register, and for the T
t
state with the lower 8 bits (CSXT7 to CSXT0).