Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 167 of 926
REJ09B0283-0300
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Invalid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
D7 to D0
Valid
Write
High
T
3
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space
(Odd Address Byte Access)