Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 161 of 926
REJ09B0283-0300
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
High impedance
Write
High
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.10 Bus Timing for 8-Bit, 2-State Access Space
