Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 160 of 926
REJ09B0283-0300
6.5.2 Valid Strobes
Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.3 Data Buses Used and Valid Strobes
Area
Access
Size
Read/
Write Address
Valid
Strobe
Upper Data Bus
(D15 to D8)
Lower Data Bus
(D7 to D0)
Byte Read — RD Valid Invalid
8-bit access
space
Write — HWR Hi-Z
Byte Read Even RD Valid Invalid16-bit access
space
Odd Invalid Valid
Write Even HWR Valid Hi-Z
Odd LWR Hi-Z Valid
Word Read — RD Valid Valid
Write — HWR, LWR Valid Valid
Notes: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
6.5.3 Basic Operation Timing
8-Bit, 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.