Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 149 of 926
REJ09B0283-0300
6.3.10 Refresh Control Register (REFCR)
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.
Bit Bit Name Initial Value R/W Description
15 CMF 0 R/(W)
*
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
• When 0 is written to CMF after reading CMF
= 1 while the RFSHE bit is cleared to 0
• When CBR refreshing is executed while the
RFSHE bit is set to 1
[Setting condition]
When RTCOR = RTCNT
14 CMIE 0 R/W Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is
performed, this bit is always cleared to 0 and
cannot be modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
13
12
RCW1
RCW0
0
0
R/W
R/W
CAS-RAS Wait Control
These bits select the number of wait cycles to
be inserted between the CAS assert cycle and
RAS assert cycle in a DRAM/synchronous
DRAM refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Note: * Only 0 can be written, to clear the flag.