Datasheet

Rev. 3.00 Mar 17, 2006 page xviii of l
7.3.7 DMA Terminal Control Register (DMATCR)..................................................... 285
7.4 Activation Sources............................................................................................................ 286
7.4.1 Activation by Internal Interrupt Request.............................................................. 287
7.4.2 Activation by External Request ........................................................................... 287
7.4.3 Activation by Auto-Request................................................................................. 288
7.5 Operation .......................................................................................................................... 288
7.5.1 Transfer Modes.................................................................................................... 288
7.5.2 Sequential Mode .................................................................................................. 290
7.5.3 Idle Mode............................................................................................................. 292
7.5.4 Repeat Mode........................................................................................................ 295
7.5.5 Single Address Mode........................................................................................... 298
7.5.6 Normal Mode....................................................................................................... 301
7.5.7 Block Transfer Mode........................................................................................... 304
7.5.8 Basic Bus Cycles.................................................................................................. 309
7.5.9 DMA Bus Cycles (Dual Address Mode) ............................................................. 310
7.5.10 DMA Bus Cycles (Single Address Mode)........................................................... 318
7.5.11 Write Data Buffer Function ................................................................................. 324
7.5.12 Multi-Channel Operation..................................................................................... 325
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,
and EXDMAC ..................................................................................................... 326
7.5.14 DMAC and NMI Interrupts.................................................................................. 327
7.5.15 Forced Termination of DMAC Operation............................................................ 327
7.5.16 Clearing Full Address Mode................................................................................ 328
7.6 Interrupt Sources............................................................................................................... 329
7.7 Usage Notes ...................................................................................................................... 330
7.7.1 DMAC Register Access during Operation........................................................... 330
7.7.2 Module Stop......................................................................................................... 331
7.7.3 Write Data Buffer Function ................................................................................. 331
7.7.4 TEND Output....................................................................................................... 332
7.7.5 Activation by Falling Edge on DREQ Pin........................................................... 333
7.7.6 Activation Source Acceptance............................................................................. 334
7.7.7 Internal Interrupt after End of Transfer................................................................ 334
7.7.8 Channel Re-Setting .............................................................................................. 334
Section 8 EXDMA Controller ......................................................................................... 335
8.1 Features............................................................................................................................. 335
8.2 Input/Output Pins.............................................................................................................. 337
8.3 Register Descriptions........................................................................................................ 338
8.3.1 EXDMA Source Address Register (EDSAR)...................................................... 338
8.3.2 EXDMA Destination Address Register (EDDAR).............................................. 339
8.3.3 EXDMA Transfer Count Register (EDTCR)....................................................... 339