Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 146 of 926
REJ09B0283-0300
• H8S/2678R Group
Bit Bit Name Initial Value R/W Description
15 DRMI 0 R/W Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when
a continuous normal space access cycle follows
a DRAM/synchronous DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
14 — 0R/WReserved
This bit can be read from or written to.
However, the write value should always be 0.
13
12
TPC1
TPC0
0
0
R/W
R/W
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
11 SDWCD 0 R/W CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tc1)
inserted by WTCR settings during synchronous
DRAM write access (see figure 6.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle
10 — 0R/WReserved
This bit can be read from or written to.
However, the write value should always be 0.