Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 145 of 926
REJ09B0283-0300
• H8S/2678 Group
Bit Bit Name Initial Value R/W Description
7 DRMI 0 R/W Idle Cycle Insertion
An idle cycle can be inserted after a DRAM
read cycle when a continuous normal space
access cycle follows a DRAM read cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS1,
ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
6 — 0R/WReserved
This bit can be read from or written to.
However, the write value should always be 0.
5
4
TPC1
TPC0
0
0
R/W
R/W
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
3, 2 — All 0 R/W Reserved
These bits can be read from or written to.
However, the write value should always be 0.
1
0
RCD1
RCD0
0
0
R/W
R/W
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted