Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 144 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
111: 11-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
• When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
The precharge-sel is A15 to A12 of the
column address.
T
p
Address
RAST = 0
RAS
RAST = 1
RAS
T
r
T
c1
T
c2
UCAS
,
LCAS
Bus cycle
Row address Column address
Figure 6.4 RAS
RASRAS
RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)
6.3.9 DRAM Access Control Register (DRACCR)
DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.
Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.